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ez-pd? ccg3 usb type-c port controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 002-03288 rev. *j revised february 23, 2018 general description ez-pd? ccg3 is a highly integrated usb type-c controller that c omplies with the latest usb type-c and pd standards. ez-pd ccg3 provides a complete usb ty pe-c and usb-power delivery port control solution for notebooks, dongles, monitors, docking stations and power adapters. ccg 3 uses cypresss proprietary m0 s8 technology with a 32-bit, 48-mhz arm ? cortex ? -m0 processor with 128-kb flash, 8-kb sram, 20 gpios, full-speed usb device c ontroller, a crypto engine for authentication, a 20v-tolerant regulator, and a pair of fets to switch a 5v (vconn) supply, wh ich powers cables. ccg3 also int egrates two pairs of gate drive rs to control external vbus fets and s ystem level esd p rotection. ccg 3 is available in 40-qfn, 32- qfn, and 42-wlcsp packages. features type-c and usb-pd support integrated usb power delivery 3.0 support integrated usb-pd bmc transceiver integrated vconn fets configurable resistors r a , r p , and r d dead battery detection support integrated fast role swap and extended data messaging supports one usb type-c port integrated hardware based over current protection (ocp) and overvoltage protection (ovp) 32-bit mcu subsystem 48-mhz arm cortex-m0 cpu 128-kb flash 8-kb sram integrated digital blocks hardware crypto block enables authentication full-speed usb device controller supporting billboard device class integrated timers and counters to meet response times required by the usb-pd protocol four run-time reconfigurable serial communication blocks (scbs) with reconfigurable i 2 c, spi, or uart functionality clocks and oscillators integrated oscillator eliminati ng the need for external clock power 2.7 v to 21.5 v operation 2x integrated dual-out put gate drivers for external vbus fet switch control independent supply voltage pin for gpio that allows 1.71 v to 5.5 v signaling on the i/os reset: 30 a, deep sleep : 30 a, sleep: 3.5 ma system-level esd protection on cc, sbu, dplus, dminus and vbus pins 8-kv contact discharge and 15-kv air gap discharge based on iec61000-4-2 level 4c packages 40-pin qfn, 32-pin qfn, and 42-ball csp for notebooks/accessories supports industrial temperature range (C40 c to +105 c)
ez-pd? ccg3 document number: 002-03288 rev. *j page 2 of 45 logic block diagram
ez-pd? ccg3 document number: 002-03288 rev. *j page 3 of 45 contents ez-pd ccg3 block diagram ...................................... ...... 4 functional overview ........................................... ............. 5 cpu and memory subsystem ..................................... 5 crypto block .................................................. .............. 5 integrated billboard device ................................... ...... 5 usb-pd subsystem (usbpd ss) . ............... .............. 5 full-speed usb subsystem ... .............. ........... .......... .. 6 peripherals ....... ........... ........... ........... ........... ............... 6 gpio .......................................................... ................. 7 power systems overview ........................................ ........ 8 pinouts ....................................................... ....................... 9 available firmware and software tools ....................... 13 ez-pd configuration utility ............. ........... ........... .... 13 ccg3 programming and bootloading .......................... 14 programming the devi ce flash over swd interface ..................................................... ................ 14 application firmware update over specific interfaces (i2c, cc, usb) ..................................... .... 14 applications .................................................. .................. 17 electrical specifications ..................................... ........... 23 absolute maximum ratings ... ................................... .23 device-level specifications . .................................. ... 24 digital peripherals ........... ........... ............ ......... .......... 26 system resources .............................................. ...... 28 ordering information .......................................... ............ 34 ordering code definitions ..................................... .... 34 packaging ..................................................... ................... 35 acronyms ...................................................... .................. 38 document conventions .......................................... ....... 39 units of measure .............................................. ......... 39 references and links to applic ations collaterals ..... 40 document history page ......................................... ........ 41 sales, solutions, and legal information ...................... 4 5 worldwide sales and design s upport ......... .............. 45 products ...................................................... .............. 45 psoc? solutions ............................................... ....... 45 cypress developer community . ................................ 45 technical support ........... .................................. ........ 45
ez-pd? ccg3 document number: 002-03288 rev. *j page 4 of 45 ez-pd ccg3 block diagram figure 1. ez-pd ccg3 block diagram [1] ccg3 32-bit ahb-lite cpu subsystem sram 8 kb sram controller rom 8 kb rom controller flash 2x64 kb read accelerator spcif deep sleep active/sleep swd/tc nvic, irqmx cortex m0 48 mhz fast mul system interconnect (single layer ahb) i/o subsystem 22 x gpios, 2 x ovts ioss gpio (3 x ports) peripherals peripheral interconnect (mmio) pclk high speed i/o matrix power modes dft logic test dft analog system resources lite power clock wdt ilo reset clock control imo sleep control pwrsys ref por wic reset control xres usb-fs fs-phy 4 x tcpwm 4 x scb crypto usb-pd ss pads, esd cc bb phy adc / aca 2 x vconn fet 2 x gate driver hv reg ovp ocp 2 x 2 analog xbar chg det note 1. see acronyms section for more details.
ez-pd? ccg3 document number: 002-03288 rev. *j page 5 of 45 functional overview cpu and memory subsystem cpu the cortex-m0 cpu in ez-pd ccg3 is part of the 32-bit mcu subsystem, which is optimized for low-power operation with extensive clock gating. it mostly uses 16-bit instructions and executes a subset of the thumb- 2 instruction set. this enables fully compatible binary upward migration of the code to higher performance processors such as the cortex-m3 and m4, thus enabling upward compatibility. the cypress implementation includes a hardware multiplier that provides a 32-bit result in one cycle. it includes a nested vecto red interrupt controller (nvic ) block with 32 interrupt inputs and also includes a wakeup interrupt controller (wic). the wic can wake the processor up from the deep sleep mode, allowing power to be switched off to the main processor when the chip is in the deep sleep mode. the cortex-m0 cpu provides a non-maskable interrupt (nmi) input, which is made available to the user when it is not in us e for system functions requested by the user. the cpu also includes a serial wire debug (swd) interface, which is a two-wire form of jtag. the debug configuration used for ez-pd ccg3 has four break -point (address) comparators and two watchpoint (data) comparators. flash the ez-pd ccg3 device has a flash module with two banks of 64 kb flash, a flash accelerator, tightly coupled to the cpu to improve average access times from the flash block. the flash block is designed to deliver 1 wait-state (ws) access time at 48 mhz and with 0-ws access time at 24mhz. the flash accelerator delivers 85% of single-cycle sram access performance on average. part of the flash module can be used to emulate eeprom ope ration if required. srom a supervisory rom that contains boot and configuration routines is provided. crypto block ccg3 integrates a crypto block for hardware assisted authentication of firmware im ages. it also supports field upgradeability of firmware in a trusted ecosystem. the ccg3 crypto block provides cryptography functionality. it includes hardware acceleration blocks for advanced encryption standard (aes) block cipher, secure hash algorithm (sha-1 and sha-2), cyclic redundancy check (crc), and pseudo random number generation. integrated billboard device ccg3 integrates a complete full s peed usb 2.0 device controller capable of functioning as a bill board class device. the usb 2.0 device controller can also s upport other device classes. usb-pd subsystem (usbpd ss) the usb-pd subsystem contains a ll of the blocks related to usb type-c and power delivery. t he subsystem consists of the following: biphase marked coding (bmc) phy: usb-pd transceiver with fast role swap (frs) transmit and detect vconn power fets for the cc lines vconn r a termination and leakers analog crossbar to switch between the sbu1/sbu2 and aux_p/aux_n pins programmable pull-up and pull-down termination on the aux_p/aux_n pins hot plug detect (hpd) processor vbus_c regulator (20v ldo) power switch between vsys supply and vbus_c regulator output vbus_c overvoltage (ov) and undervoltage (uv) detectors current sense amplifier (csa) for overcurrent detection gate drivers for vbus_p and vbus_c external power fets vbus_c discharge switch usb2.0 full-speed (fs) phy with integrated 5.0 v to 3.3 v regulator charger detection/emulation for usb bc1.2 and other proprietary protocols two instances of 8-bit sar adcs 8-kv iec esd protection on the following pins: vbus_c, cc1, cc2, sbu1, sbu2, dp, dm the ez-pd ccg3 usb-pd subsystem interfaces to the pins of a usb type-c connector. it includes a usb type-c baseband transceiver and physical-layer logic. this transceiver performs the bmc and the 4b/5b encoding a nd decoding functions as well as integrating the 1.2-v analo g front end (afe). this subsystem integrates the required terminations to identify the role of th e ccg3 device, including r p and r d for ufp/dfp roles and r a for emca/vconn powered accessories. the programmable vconn leakers are included to discharge vconn capacitance during a disconnect event. it also integrates power fets for supplying vconn power to the cc1/cc2 pins from the v5v pin. the analog crossbar enables connecting either of the sbu1/sbu2 pins to either of the aux_p/aux_n pins to support displayport sideband signaling. the integrated hpd processor can be used to control or monitor the hpd signal of a displaypo rt source or sink.
ez-pd? ccg3 document number: 002-03288 rev. *j page 6 of 45 the overvoltage/undervoltage (ov/uv) block monitors the vbus_c supply for programmable overvoltage and undervoltage conditions. the cs a amplifies the voltage across an external sense resistor, which is proportional to the curren t being drawn from the external dc-dc vbus supply converter. the csa output can either be measured with an adc or configured to detect an overc urrent condition. the vbus_p and vbus_c gate drivers control the gates of external power fets for the vbus_c and vbus_p supplies. the gate drivers can be configured to support both p and n type external power fets. the gate drivers are configured by default for nfet devices. in applications using pfets, the gate drivers must be appropriatel y configured. the ov/uv and csa blocks can generate interrupts to automatically turn off the power fets for the programmed overvoltage and overcurrent conditions. the vbus_c discharge switch allows for discharging the vbus_c line through an external resistor. the usb-pd subsystem also c ontains two 8-bit successive approximation register (sar) adcs for analog to digital conversions. the voltage refer ence for the adcs is generated from the vddd supply. each adc includes an 8-bit dac and a comparator. the dac output forms the positive input of the comparator. the negative input of the comparator is from a 4-input multiplexer. the four inputs of the multiplexer are a p air of global analog multiplex busses, an internal bandgap voltage and an internal voltage proportional to the absolute temperatur e. each gpio pin can be connected to the global analog multiplex busses through a switch, which allows either adc to sample the pin voltage. when sensing the gp io pin voltage with an adc, the pin voltage cannot exceed the vddio supply value. figure 2. usb-pd subsystem full-speed usb subsystem the fsusb subsystem contains a full-speed usb device controller as described in the integrated billboard device section. peripherals serial communication blocks (scb) ez-pd ccg3 has four scbs, which can be configured to implement an i 2 c, spi, or uart interface. the hardware i 2 c blocks implement full multi-master and slave interfaces capable of multimaster arbitration. in the spi mode, the scb blocks can be configured to act as master or slave. in the i 2 c mode, the scb blocks are capable of operating at speeds of up to 1 mbps (fast mode plus) and have flexible buffering options to reduce interrupt overhead and latency for the cpu. these blocks also support i 2 c that creates a mailbox address range in the memory of ez-pd ccg3 and effectively reduce i 2 c communication to reading from and writing to an array in memory. in addition, the blocks suppor t 8-deep fifos for receive and transmit which, by increasing the time given fo r the cpu to read data, greatly reduce the need for clock stretching caused by the cpu not having read data on time. the i 2 c peripherals are compatible with the i 2 c standard-mode, fast-mode, and fast-mode plus devices as defined in the nxp i 2 c-bus specification and user manual ( um10204 ). the i 2 c bus i/os are implemented with gpio in open-drain modes. vbus_c v5v ldo power switch charger dc-dc ov/uv oc csa usb type-c port vsys vddd ra vconn leaker producer n/pfets vbus_p_ctrl gate driver gate driver vbus_c_ctrl vbus_discharge charger detect analog cross-bar programmable pull-up, pull-down aux_p aux_n usb 2.0 fs phy bmc phy w/ frs vbus_p vconn switch consumer n/pfets cc1 cc2 sbu1 sbu2 dp dm usb pd subsystem 2x adcs hpd hpd
ez-pd? ccg3 document number: 002-03288 rev. *j page 7 of 45 the i 2 c port on scb 1-3 blocks of ez-pd ccg3 are not completely compliant with the i 2 c specification in the following aspects: t h e g p i o c e l l s f o r s c b 1 ' s i 2 c port are not ove rvoltage-tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the i 2 c system. fast-mode plus has an i ol specification of 20 ma at a v ol of 0.4 v. the gpio cells can sink a maximum of 8-ma i ol with a v ol maximum of 0.6 v. fast-mode and fast-mode plus specify minimum fall times, which are not met with the gpio cell; slow strong mode can help meet this spec dep ending on the bus load. timer/counter/pwm block (tcpwm) ez-pd ccg3 has four tcpwm blocks. each implements a 16-bit timer, counter, pulse-width modulator (pwm), and quadrature decoder functionality. gpio ez-pd ccg3 has up to 20 gpios (these gpios can be configured for gpios, scb, sbu, and aux signals) and swd pins, which can also be used as gpios. the i 2 c pins from scb 0 are overvoltage-tolerant. the gpio block implements the following: seven drive strength modes: ? input only ? weak pull-up with strong pull-down ? strong pull-up with weak pull-down ? open drain with strong pull-down ? open drain with strong pull-up ? strong pull-up with strong pull-down ? weak pull-up with weak pull-down input threshold select (cmos or lvttl) individual control of input and o utput buffer enabling/disablin g in addition to the drive strength modes hold mode for latching previous state (used for retaining i/o state in deep sleep mode) selectable slew rates for dv/dt related noise control to improv e emi during power-on and reset, the i/o pins are forced to the disab le state so as not to crowbar any inputs and/or cause excess turn-on current. a multiplexing network known as a high-speed i/o matrix is used to multiplex b etween various signals that ma y connect to an i/o pin.
ez-pd? ccg3 document number: 002-03288 rev. *j page 8 of 45 power systems overview figure 3 shows an overview of the ccg3 power system requirement. ccg3 shall be able to operate from two possible external supply sources vbus (4.0 vC21.5 v) or vsys (2.7 vC 5.5 v). the vbus supply is regulated inside the chip with a low-dropout regulator (ldo) down to 3.3-v level. the chips internal vddd rail is intelligen tly switched between the output of the vbus regulator and unreg ulated vsys. the switched supply, vddd is either used directly inside some analog blocks or further regulated down to vcc d which powers majority of the core using regulators. besides reset mode, ccg3 has three different power modes: active, sleep and deep sleep, transitions between which are managed by the power system. a separate power domain vddio is provided for the gpios. the vddd and vccd pins, both the output of regulators are brought out for connecting a 1-f capacitor for the regulator stability only. these pins are not supported as power supplies. when ccg3 is powered from vsys that is grea ter than 3.3 v, the dedicated usb regulator allows usb operation. figure 3. ez-pd ccg3 power system block diagram table 1. ccg3 power modes mode description reset power is valid and xres is not asserted. an internal reset sour ce is asserted or sleepcontroller is sequencing the system out of reset. active power is valid and cpu is executing instructions. sleep power is valid and cpu is not executing instructions. all logic that is not operating is clock gated to save power. deep sleep main regulator and most hard-ip are shut off. deep sleep regula tor powers logic, but only low-frequency clo ck is available. vss vbus vddd regulator vsys vccd core vddio gpio cc tx/rx ccg3 cc1, cc2 vconn vss ldo switch fs-usb tx/rx dp, dm r a ovp gate driver vbus_c_ctrl ocp gate driver vbus_p_ctrl vbus_p oc vbus_discharge 1uf 1uf 1uf 1uf usb regulator
ez-pd? ccg3 document number: 002-03288 rev. *j page 9 of 45 pinouts table 2. ccg3 pin description for 42-csp, 32-qfn, and 40-qfn d evices pin map 42-csp pin map 32-qfn pin map 40-qfn name description a5 1 1 vbus_p_ctrl1 vbus gate driver control 1 for producer switch a6 1 2 vbus_p_ctrl0 vbus gate driver control 0 for producer switch b6 2 3 cc2 usb pd connector detect/configuration channel 2 c5 n/a n/a cc2 usb pd connector detect/configuration channel 2 d4 3 4 v5v input supply voltage for vconn fets v5v = 5.0v C 5.5v to supply vconn > 4.75v @ 1.5w v5v = 3.5v C 5.5v to supply vconn > 3.00v @ 1w c6 4 5 cc1 usb pd connector detect/configuration channel 1 d6 n/a n/a cc1 usb pd connector detect/configuration channel 1 e6 n/a 6 vconn vconn input - provides r a termination for cable applications f6 5 7 p1.0 gpio/uart_2_tx / spi_2_miso d5 n/a 8 p1.1 gpio/uar t_2_rx / spi_2_sel e5 6 9 p1.2 gpio/uart_0_rx/ uart_3_cts/ spi_3_mosi/ i2c_3_scl g6 7 10 p1.3 gpio/uart_0_tx/ uart_3_rts/ spi_3_clk/ i2c_3_sda e4 n/a 11 aux_p / p1.6 displayport aux_p signal / gpio / uart_1_tx / spi_1_miso f5 8 12 sbu1 / p1.4 usb type-c sbu1 signal / gpio / uart_3_tx/ spi_3_miso/ swd_1_clk g5 9 13 sbu2 / p1.5 usb type-c sbu2 signal / gpio / uart_3_rx/ spi_3_sel/ swd_1_dat g4 n/a 14 aux_n / p1.7 displayport aux_n signa l / gpio / uart_1_rx / spi_1_sel f4 10 15 p2.0 gpio / uart_1_cts / s pi_1_clk/ i2c_1_scl / swd_0_dat g3 11 16 p2.1 gpio / uart_1_rts / spi_1_mosi/ i2c_1_sda / swd_0_clk g2 13 17 vddd vddd supply input / output (2.7 vC5.5 v) f3 14 18 vddio 1.71 vC5.5 v supply for i/os. t his supply also powers the global analog multiplex buses. f2 15 19 vccd 1.8-v regulator output for filter capacitor g1 16 20 vsys system power supply (2.7 vC5.5 v) f1 17 21 dplus usb 2.0 dp e1 18 22 dminus usb 2.0 dm e2 19 23 p2.4 gpio d3 20 24 p2.5 gpio / uart_0_tx/ spi_0_mosi d2 n/a 25 p2.6 gpio / ua rt_0_rx/ spi_0_clk d1 21 26 xres external reset input . internally pulled-up to vddio. c3 22 27 p0.0 i2c_0_sda / gpio_ovt / uart_0_cts / spi_0_sel/ tcpwm0
ez-pd? ccg3 document number: 002-03288 rev. *j page 10 of 45 c2 23 28 p0.1 i2c_0_scl / gpio_ovt / ua rt_0_rts / spi_0_miso/ tcpwm1 c1 24 29 vbus_c_ctrl1 vbus gate driver control 1 for consumer switc h c4 24 30 vbus_c_ctrl0 vbus gate driver control 0 for consumer switc h b1 25 31 vbus vbus input a1 26 32 vbus_discharge vbus discharge control output e3 12, 27 33 vss ground supply (gnd) epad epad vss a2 28 34 p3.2 gpio / tcpwm0 b2 n/a 35 p3.3 gpio / tcpwm1 b3 29 36 p3.4 gpio / uart_2_cts / spi_2_mosi/ i2c_2_sda / tcpwm2 a3 30 37 p3.5 gpio / uart_2_rts / spi_2_clk/ i2c_2_scl / tcpwm3 b4 n/a 38 p3.6 gpio a4 31 39 oc overcurrent sensor input b5 32 40 vbus_p vbus producer input table 2. ccg3 pin description for 42-csp, 32-qfn, and 40-qfn d evices (continued) pin map 42-csp pin map 32-qfn pin map 40-qfn name description
ez-pd? ccg3 document number: 002-03288 rev. *j page 11 of 45 figure 4. pinout of 40-qfn package (top view) figure 5. pinout of 32-qfn package (top view) 1 2 3 4 5 6 vbus_p_ctrl1 vbus_p_ctrl0 cc2 v5v cc1 vconn 30 29 28 27 26 25 vbus_c_ctrl0 vbus_c_ctrl1 gpio_ovt gpio_ovt xres gpio 40 39 38 37 36 35 vbus_p oc gpio gpio gpio gpio 7 8 9 10 gpio gpio gpio gpio 11 12 13 14 15 16 aux_p sbu1 sbu2 aux_n gpio gpio 17 18 19 20 vddd vddio vccd vsys 24 23 22 21 gpio gpio dminus dplus 34 33 32 31 gpio gnd vbus_discharge vbus epad epad 32 31 30 29 vbus_p oc gpio gpio 28 27 26 25 gpio vss vbus_discharge vbus 9 10 11 12 13 14 sbu2 gpio gpio vss 15 16 vddd vddio vccd vsys 1 2 3 4 5 6 vbus_p_ctrl cc2 v5v cc1 7 8 gpio gpio gpio sbu1 24 23 22 21 vbus_c_ctrl gpio_ovt gpio_ovt xres 20 19 18 17 gpio gpio dminus dplus
ez-pd? ccg3 document number: 002-03288 rev. *j page 12 of 45 figure 6. pinout of 42-wlcs p bottom (balls up) view a b c d e f g 1 2 3 4 5 6 vbus_p_ct rl0 vbus_p_ct rl1 oc gpio p3.5 gpio p3.2 vbus_disc harge cc2 vbus_p gpio p3.6 gpio p3.4 gpio p3.3 vbus cc1 cc2 vbus_c_ct rl0 gpio_ovt p0.0 gpio_ovt p0.1 vbus_c_ct rl1 cc1 gpio p1.1 v5v gpio p2.5 gpio p2.6 xres vconn gpio p1.2 aux_p vss gpio p2.4 dminus gpio p1.0 sbu1 gpio p2.0 vddio vccd dplus gpio p1.3 sbu2 aux_n gpio p2.1 vddd vsys
ez-pd? ccg3 document number: 002-03288 rev. *j page 13 of 45 available firmware and software tools ez-pd configuration utility the ez-pd configuration utility is a gui-based microsoft window s application developed by cypress to guide a ccgx user through the process of configuring and programming the chip. the utilit y allows users to: 1. select and configure the pa rameters they want to modify 2. program the resulting configur ation onto the ta rget ccgx devi ce. the utility works with the cypre ss supplied ccg1, ccg2, ccg3, a nd ccg4 kits, which host the ccgx controllers along with a usb interface. this version of the e z-pd configuration utility supp orts configuration and firmware update operations on ccgx contr ollers implementing emca and display dongle applications. support for other applications, such as po wer adapters and notebook port controllers, will be provided in later versions of the utility. you can download the ez-pd conf iguration utility and its associ ated documentation at the following link: http://www.cypress.com/ documentation/software-and-drivers/ez-pd -configuration-utility
ez-pd? ccg3 document number: 002-03288 rev. *j page 14 of 45 ccg3 programming and bootloading there are two ways to program application firmware into a ccg3 device: 1. programming the device flash over swd interface 2. application firmware update over specific interfaces (cc, usb, i 2 c) generally, the ccg3 devices are programmed over swd interface only during developmen t or during the manufacturing process of the end product. once the end product is manufac- tured, the ccg3 device's applicat ion firmware can be updated via the appropriate bootloader interface. programming the device fl ash over swd interface the ccg3 family of devices can be programmed using the swd interface. cypre ss provides a pr ogramming kit ( cy8ckit-002 miniprog3 kit ) called miniprog3 which can be used to program the flash as well as debug firmware. the flash is programmed by downloading the information from a hex file. this hex file is a binary file generated as an output of building the firmware pro ject in psoc creator software . click here for more information on how to use the min iprog3 programmer. there are many third-party programmers that support mass programming in a manufacturing environment. as shown in the block diagram in figure 7 , the swd_0_dat and swd_0_clk pins are connected to the host programmer's swdio (data) and sw dclk (clock) pins respectively. during swd programming, the device can be powered by the host programmer by connecting it s vtarg (power supply to the target device) to vsys pin of ccg3 device. if the ccg3 device is powered using an on-board power supply, it can be programmed using the reset p rogramming option. for more details, refer to the cypd3xxx programming specifications. the cypd3105 device for thunderbolt cable applications is pre-programmed with a micro-b ootloader that allows users to program the flash using the alternate swd pins (sbu1 for swd_1_clk and sbu2 for swd_1_dat) that can be connected to the sbu interface of a type-c connector. note that this interface can be used to program the flash only once. subs e- quent re-programming of this device can be done through the primary swd interface (swd_0_clk and swd_0_dat pins). irrespective of which swd interf ace is used for programming the device, once the device is programmed with the hex file provide d by cypress for thunderbolt cable application, subsequent updates to the application fi rmware can be d one over the cc line. refer to application firmware up date over specific inter- faces (i2c, cc, usb) for more details. figure 7. connecting the programmer to cypd3xxx device application firmware update over specific interfaces (i 2 c, cc, usb) the application firmware can be updated over t hree different interfaces depending on the default firmware programmed into the ccg3 device. refer to ta b l e 3 8 for more detai ls on default firmware that various part num bers of the ccg3 family of devices are pre-programmed with (note that some of the devices have bootloader only and some have bootloader plus application firmware). the application firmwar e provided by cypress for all ccg3 applications have dual im ages. this allows fail-safe update of the alternat e image while executing from the current image. for more information, refer to the ez-pd configuration utility user manual . application firmware update over i 2 c interface this method primarily applie s to cypd3122, cypd3125, and cypd3126 devices of the ccg3 family. in these applications, the ccg3 device interfaces to an on-board application processor or an embedded controller over i 2 c interface. refer to figure 8 for more details. cypress provides pseudo-code for the host processor for updating the ccg3 device firmware. host programmer cypd3xxx v dd vsys swdclk xres swdio gnd swd_0_clk xres swd_0_dat v dd gnd v ss 3.0 v v ccd v ddd v ddio 1 ? f 10v x7r 1 ? f 10v x7r
ez-pd? ccg3 document number: 002-03288 rev. *j page 15 of 45 figure 8. application firmware update over i 2 c interface application firmware update over cc line this method primarily applies to the cypd3135 device of the ccg3 family. in these applications, the cy4531 ccg3 evk can be used to send programming and configuration data as cypress specific vendor defined messages (vdms) over the cc line. the cy4531 ccg3 evk is connected to the system containing the ccg3 device on one end and a windows pc running the ez-pdtm configuration utility as shown in figure 9 on the other end to program the ccg3 device. figure 9. application firmware update over cc line application firmware update over usb this method primarily applies to the cypd3120 and cypd3121 devices of the ccg3 family. in these applications, the firmware update can be performed over the d+/d- lines (usb2.0) using various possible options as shown in figure 10 . option 1 is to have a windows pc running ez-pd ? configuration utility connected to the device to be programmed via the cy4531 ccg3 evk. this setup can be avoi ded using option 2, where the user has a type-a to type-c cable. this option requires that th e system contain the ccg3 device to be programm ed to have a type-c receptacle. the other option (option 3) is to have a windows pc with a native type-c connector as shown in figure 10 . embedded controller/ application processor 2.2k ? 2.2k ? 2.2k ? vddd cypd3xxx device to be programmed i2c_sda i2c_scl i2c_int pc running ez-pd configuration utility cy4531 ccg3 evk cypd3135 device to be programmed usb serial device of ccg3 daughter card cc line usb mini-b cable ccg3 device on ccg3 daughter card i 2 c mini-b receptacle type-c receptacle
ez-pd? ccg3 document number: 002-03288 rev. *j page 16 of 45 figure 10. application firmware update over usb pc running ez-pd configuration utility cy4531 ccg3 evk cypd 312x device to be programmed usb type-a to type-b cable d+/d- pc running ez-pd configuration utility cypd 312x device to be programmed usb type-a to type-c cable windows pc with native type-c connector running ez-pd configuration utility cypd 312x device to be programmed type-b receptacle type-c receptacle or or option 1 option 2 option 3 type-c receptacle type-c plug
ez-pd? ccg3 document number: 002-03288 rev. *j page 17 of 45 applications figure 11 illustrates the application diagram of a power adapter using a ccg3 device. in this application, ccg3 is used as dfp (power provider) only. the maximum power profile that can be supported by power adapters is up to 20 v, 100 w using 40-pin qfn ccg3 devices. ccg3 has the ability to drive both types of fets and the state of gpio p1.0 (floating or grounded) indicate s the type of fet (n-mos or p-mos fet) being used in the power provider path. ccg3 integrates all termination resistors and uses gpios (vsel0 and vsel1) to indicate the negotiated power profile. if required, the power profile can also be selected using ccg3 serial interfaces (i 2 c, spi) or pwm. the vbus voltage on the type-c port is monitored using internal circuits to detect unde r- voltage and overvoltage conditions. to ensure quick discharge of vbus when the power adapter cable is detached, a discharge path is provided with a resistor connected to the vbus_dis- charge pin of the ccg3 device. overcurrent protection is enabled by sensing the current throug h the 10-m ? sense resistor using the oc and vbus_p pins of the ccg3 device. the vbus provider through the type-c connector can be turned on or off using the provider path fets. the power provider fets are controlled by high-voltage gate driver outputs (vbus_p_ctrl0 and vbus_p_ctrl1 pins of ccg3 device). the ccg3 device is also capable of supporting proprietary charging protocols over the dp and dm lines of the type-c receptacle. by providing a 5-v source at the v5v pin of the ccg3 device, the device becomes capable of delivering the vconn supply over either the cc1 or cc2 pins of the type-c connector. the ccg3 family's power adapter parts are shipped with bootloader and application firmware with limited functionality. its purpose is to facilitate applicat ion flashing over cc line usin g the ez-pd configuration utility. the power adapter requires an explicit power contract to be negotiated prior to enabling the ez-pd configuration utility to flash the application firmware. this application firmware, based on the state of the gpio (p1.0), determines the type of provider load switch (nfet/pfet) and supplies the 5-v vbus over type-c. figure 11. power adap ter application diagram (40-qfn device) cypd3135-40lqxit 40qfn vsel2/p0.0 28 vsel1/p0.1 27 dc/dc or ac-dc secondary (5-20v) vsel2 vsel1 vbus_p 40 vbus 31 1 ? f 50v x7r gnd 33 vbus_p_ctrl1 cc2 cc1 vbus_discharge 1 32 3 5 type-c receptacle vsys 20 vddd vddio 17 18 1 ? f 10v x7r 390pf 5% x7r 390pf 5% x7r 2 vbus_p_ctrl0 100 ? 10 ? f 50v 26 xres 19 vccd 1.3 ? f 10v x7r 0.1 ? f cc2 cc1 dplus dminus 22 21 12 sbu1 13 sbu2 aux_p 11 aux_n 14 gpio 8, 9, 10, 15, 16, 24, 25, 34, 35, 36, 37, 38 vbus_c_ctrl1 29 vbus_c_ctrl0 30 10 m ? 1% 39 oc vbus_oc dmn3018ssd-13 dmn3018ssd-13 v5v p2.4 23 4 d g s s g d 5v vbus gnd vbus_out vbus_in x x x xx x x 10m ? 10m ? 100k ? 10k ? vbus_out vconn 6 x 7 p1.0 x p1.0 indicates fet type in design. floating condition indicates nfets and connected to gnd indicates pfets in provider path.
ez-pd? ccg3 document number: 002-03288 rev. *j page 18 of 45 figure 12 illustrates a power bank app lication diagram using a ccg3 device. in this application, the type-c receptacle is used for providing as well as consuming power. the consumer path will be active when the battery is charged using a type-c power source that is connected to the type-c receptacle in figure 12 . the provider path will be active when the power bank is used fo r providing power to a sink device connected to the type-c recep- tacle. additionally, a type-a receptacle can also be provided f or providing power to the sinks that have a legacy usb interface. the ccg3 device negotiates power contracts between the power bank and the sink/source device connected to the type-c receptacle. the ccg3 device also controls and drives the provider and consumer path fets and can monitor overcurrent and overvoltage conditions on the type-c vbus line. figure 12. power bank appli cation diagram (40-qfn device) cypd3121-40lqxit 40qfn vddd 17 vddio 18 vbus_c_ctrl0 cc2 cc1 vbus_discharge 30 32 3 5 gpio/sbu1 12 gpio/sbu2 i2c_scl/gpio 13 37 390pf 5% x7r 2 vbus_p_ctrl0 100 ? 35 gpio 19 vccd 1uf 10v x7r aux_p/gpio aux_n/gpio 14 11 9 i2c_ scl/gpio 10 39 oc dplus dminus 22 21 type-c receptacle cc2 cc1 ccg3 gpio 10 ? f 50v dmn3018ssd-13 dmn3018ssd-13 10 m ? 1% 1 ? f 35v x7r 1 vbus_p_ctrl1 vbus_c_ctrl1 29 dmn3018ssd-13 dmn3018ssd-13 power subsystem + battery 390pf 5% x7r vconn 6 v5v 4 vbus 31 vbus_p 40 vsys 20 1 ? f 10v 0.1 ? f 10v 0.1 ? f 10v 0.1 ? f 10v x7r 1 ? f 10v 0.1 ? f 10v 0.1 ? f 10v i2c_sda/gpio 36 gpio 34 ccg3 gate driver control configuration needs to be appropr iately set, based on the vbus fet type (nfet/pfet). s g d d g s d g s s g d 7, 8, 15, 16, 23, 24, 25, 27, 28, 38 xres gnd 33 26 gpio vbatt vbus vbus vbus gnd dp ss i2c_ sda/gpio x x x x x 10m ? 10m ? 10m ? 10m ? x dn consumer path provider path x type-a receptacle vbus gnd dp dn discrete ckts to support legacy charge source from power subsystem
ez-pd? ccg3 document number: 002-03288 rev. *j page 19 of 45 figure 13 illustrates a usb type-c to displayport (4-lane) adapter appli cation, which enables connectivity between a pc that supports a type-c port with displayport alternate mode support and a leg acy monitor that has a displayport interface. the application meets the requirements described in section 4.2 of the vesa displayport alt mod e on usb type-c standard versio n 1.0 (scenarios 2a and 2b usb type-c to displayport cables). figure 13. usb type-c to displayport adapter application diagr am CYPD3120-40LQXIT 40qfn vddd 17 vddio 18 vbus_c_ctrl0 cc2 cc1 vbus_discharge 30 32 3 5 aux_p 11 aux_n i2c_scl / p3.5 14 37 390pf 5% x7r 2 vbus_p_ctrl0 23 p2.4 19 vccd 1 ? f 10v x7r sbu1 sbu2 13 12 9 mux_i2c_ scl/p1.2 10 39 oc dplus dminus 22 21 type-c plug vconn cc 1 vbus_p_ctrl1 vbus_c_ctrl1 29 vconn 6 v5v 4 vbus 31 vbus_p 40 vsys 20 1 ? f 10v 0.1 ? f 10v 0.1 ? f 10v x7r 1 ? f 10v i2c_sda / p3.4 36 i2c_int / p3.2 34 7, 8, 15, 16, 24, 25, 27, 28, 38 xres gnd 33 26 gpio vconn vbus gnd dp ss mux_i2c_ sda/p1.3 1 ? f 10v 1 ? f 10v 0.1 ? f 10v dn sbu1 sbu2 0.1 ? f 10v mdp/ dp display port data lanes hotplug detect hotplug_det / p3.3 35 x p2.4 indicates type of end application. floating condition indicates usage for type-c to dp application and connected to gnd indicates usage for type-c to hdmi adapter application.
ez-pd? ccg3 document number: 002-03288 rev. *j page 20 of 45 figure 14 illustrates a usb type-c to hdm i adapter application, which en ables connectivity between a pc that supports a type-c port with displayport alternate mode support and a legacy monit or that has hdmi interface. it enables users of any notebook th at implements usb-type c to connect to other display types. this application meets the requirements described in section 4. 3 of the vesa displayport alt mode on usb type-c standard versi on 1.0. this application supports display output at a resolution o f up to 4k ultra hd (3840x2160) at 60 hz. figure 14. usb type-c to hdmi adapter application CYPD3120-40LQXIT 40qfn vddio 18 vddd 17 vbus_c_ctrl0 cc2 cc1 vbus_discharge 30 32 3 5 aux_p 11 aux_n i2c_scl / p3.5 14 37 390pf 5% x7r 2 vbus_p_ctrl0 35 hotplug_ det / p3.3 19 vccd 1uf 10v x7r sbu1 sbu2 13 12 9 mux_i2c_ scl/p1.2 10 39 oc dplus dminus 22 21 type-c plug vconn cc 1 vbus_p_ctrl1 vbus_c_ctrl1 29 vconn 6 v5v 4 vbus 31 vbus_p 40 vsys 20 1uf 10v 0.1uf 10v 0.1uf 10v x7r 1uf 10v i2c_sda / p3.4 36 i2c_int / p3.2 34 7, 8, 15, 16, 24, 25, 27, 28, 38 xres gnd 33 26 gpio vconn vbus gnd dp ss mux_i2c_ sda/p1.3 1uf 10v 1uf 10v 0.1uf 10v dn sbu1 sbu2 0.1uf 10v hdmi/ dvi/ vga display port data lanes aux_p/n hotplug detect dp to hdmi/ dvi/vga convertor power or 5v regulator buckboost p2.4 23 5v buckboost not needed for dvi/vga p2.4 indicates type of end application. floating condition indicates usage for type-c to dp application and connected to gnd indicates usage for type-c to hdmi adapter application. 3.3v 1.2v 3.3v 1.2v 3.3v vconn vbus
ez-pd? ccg3 document number: 002-03288 rev. *j page 21 of 45 figure 15 illustrates a notebo ok drp application di agram using a ccg3 de vice. the type-c port can be used as a power provider or a power consumer. the ccg3 device communicates with the embe dded controller (ec) over i 2 c. it also controls the data mux to route the highspeed signals either to the usb chipset (during n ormal mode) or the displayport chipset (during alternate mode). the sbu, superspeed, and highspeed lines are routed directly from t he display mux of the notebook to the type-c receptacle. figure 15. drp app lication diagram cypd3125-40lqxit 40qfn vddd 17 vddio 18 vbus_c_ctrl0 cc2 cc1 vbus_discharge 30 32 3 5 sbu1 12 sbu2 i2c_scl / p3.5 13 37 390pf 5% x7r 2 vbus_p_ctrl0 100 ? 35 hotplug_ det / p3.3 19 vccd 1uf 10v x7r aux_p aux_n 14 11 9 mux_i2c_ scl/p1.2 10 39 oc dplus dminus 22 21 type-c receptacle cc2 cc1 embedded controller displayport chipset hpd dp0/1/2/3 aux+/- usb chipset d+/- ss data mux ss hs/ss/ dp/sbu lines d+/- 10uf 50v dmn3018ssd-13 dmn3018ssd-13 10 m ? 1% dc/dc 1uf 35v x7r 1 vbus_p_ctrl1 vbus_c_ctrl1 29 dmn3018ssd-13 dmn3018ssd-13 charger 390pf 5% x7r vconn 6 v5v 4 vbus 31 vbus_p 40 vsys 20 1uf 10v 0.1uf 10v 0.1uf 10v 0.1uf 10v x7r 1uf 10v 0.1uf 10v 0.1uf 10v hpd i2c_sda / p3.4 36 i2c_int / p3.2 34 v3p3 and v5p0 are 3.3v and 5v supplies coming from the motherboard. ccg3 gate driver control configuration needs to be appropriately set, based on the vbus fet type (nfet/pfet). s g d d g s d g s s g d 2.2k ? 2.2k ? 2.2k ? 7, 8, 15, 16, 23, 24, 25, 27, 28, 38 xres gnd 33 26 gpio v3p3 vbus vbus v5p0 vint20 vbus_supply vbus gnd dp/dn ss mux_i2c_ sda/p1.3 scl sda x x x x x 10m ? 10m ? 10m ? 10m ? vddd vddd
ez-pd? ccg3 document number: 002-03288 rev. *j page 22 of 45 figure 16 illustrates a ccg3 devic e based charge-through dongle application block diagram. this charge-through dongle application also implements cypresss usb superspeed hub controller hx3 (cyusb3304-68ltxi) available in 68-qfn package, low-power single chip usb 3.0 to gigabit ethernet bridge controller gx3 (cyusb3610-68ltxc) available in 68-qfn package and the ccg2 (cypd2122-24lqxi) which acts as an upstream facing port (ufp) and sinks power when connected to usb type-c chargers. this application enables connectivity between a usb type-c notebook and hdmi display, legacy usb device and gigabit ethernet while also connecting a usb type-c charging cable. the charge-through dongle solution allows simultaneous hdmi display, superspeed data transfers, ethernet connection and charging of a usb type-c notebook. charge-through dongle is also widely known as multiport adapter. more details including the schematic of the ccg3 device based charge-through dongle reference design can be found here . figure 16. charge-through dongle application block diagram (40 -qfn device) type-c plug type-c receptacle for charging from dfp charger usb3.1 type-a receptacle cc vconn_n hs lines vbus_a vbus_c legacy usb devices cc hdmi receptacle dp to hdmi protocol convertor megachips mcdp2900 2x lane dp 8 cypress hx3 c y u s b 3 3 0 4 cyusb3304 68-qfn ss lines ss/hs lines 3.3v 1.2v 5v vbus_n i2c to display power 5.0v 3.3v 1.2v vbus_c vbus_n ds1 ds3 to notebook ccg2 ufp cypd2122 24-qfn vconn_n ccg3 drp cypd3123 40-qfn hs lines 4 4 ethernet port ds2 3.3v 1.2v 5v cypress gx3 cyusb3610 68-qfn
ez-pd? ccg3 document number: 002-03288 rev. *j page 23 of 45 electrical specifications absolute maximum ratings table 3. absolute maximum ratings parameter description min typ max units details/conditions v sys_max digital supply relative to v ss C0.5 C 6 v absolute max v 5v max supply voltage relative to v ss CC 6 v v bus_max_on max supply voltage relative to v ss , v bus regulator enabled CC 26 v v bus_max_off max supply voltage relative to v ss , v bus regulator enabled 100% of the time CC 24.5 v max supply voltage relative to v ss , v bus regulator enabled 25% of the time CC 26 v v ddio_max max supply voltage relative to v ss CC 6 v v gpio_abs gpio voltage C0.5 C vddio + 0.5 v v gpio_ovt_abs ovt gpio voltage C0.5 C 6 v i gpio_abs maximum current per gpio C25 C 25 ma v conn_max max voltage relative to v ss CC 6 v v cc_abs max voltage on cc1 and cc2 pins C C 6 v i gpio_injection gpio injection current, max for v ih > vddd, and min for v il < v ss C0.5 C 0.5 ma absolute max, current injected per pin esd_hbm electrostatic discharge human body model 2200 C C v C esd_cdm electrostatic discharge charged device model 500 C C v C lu pin current for latch-up C100 C 100 ma tested at 125 c esd_iec_con electrostatic discharge iec61000-4-2 8000 C C v contact discharge on cc1, cc2, vbus, dplus, dminus, sbu1 and sbu2 pins esd_iec_air electrostatic discharge iec61000-4-2 15000 C C v air discharge for cc1, cc2, vbus, dplus, dminus, sbu1 and sbu2 pins
ez-pd? ccg3 document number: 002-03288 rev. *j page 24 of 45 device-level specifications all specifications are valid for C40 c ? t a ? 105 c and t j ? 120 c, except where noted. table 4. dc specifications spec id parameter description min typ max units details/conditions sid.pwr#1 vsys C 2.7 C 5.5 v ufp mode. sid.pwr#1_a vsys C 3 C 5.5 v dfp/ drp or gate driver modes sid.pwr#23 vconn power supply input voltage 2.7 C 5.5 v C sid.pwr#13 vddio io supply voltage 1.71 C 5.5 [2] v 2.7v < vddd < 5.5 v sid.pwr24 vccd output voltage for core logic C1.8C v C sid.pwr#4 idd supply current C 25 C ma from vsys or vbus vbus = 5v, t a = 25 c / vsys = 5 v, ta = 25 c fs usb, cc io in tx or rx, no i/o sourcing current, 2 scbs at 1 mbps, cpu at 24 mhz. sid.pwr#1_b vsys power supply for usb operation 4.5 C 5.5 v usb configured, usb regulator enabled sid.pwr#1_c vsys power supply for usb operation 3.15 C 3.45 v usb configured, usb regulator disabled sid.pwr#1_d vsys power supply for charger detect/emulation operation 3.15 C 5.5 v C40 c to +85 c t a sid.pwr#27 vbus power supply input voltage 3.5 C 21.5 v fs usb disabled. total current consumption from vbus <15 ma. sid.pwr#28 vbus power supply input voltage for usb operation 4.5 C 21.5 v fs usb configured, usb regulator disabled sid.pwr#30 vbus_p power supply input voltage 4.00 C 21.5 v sid.pwr#15 c efc external regulator voltage bypass for vccd 11.31.6 f x5r ceramic or better sid.pwr#16 c exc power supply decoupling capacitor for vsys 0.8 1 C f x5r ceramic or better sleep mode. vsys = 2.7 v to 5.5 v. typical values measured at v dd = 3.3 v and ta = 25 c. sid25a i dd20a cc, i 2 c, wdt wakeup on. imo at 48 mhz. C3.5Cma vsys = 3.3 v, t a = 25 c, all blocks except cpu are on, cc io on, usb in suspend mode, no i/o sourcing current deep sleep mode sid_ds i dd_ds vsys = 3.0 to 3.6 v. cc attach, i 2 c, wdt wakeup on. C30C a power source = vsys, dfp mode, type-c not attached. cc attach, i 2 c and wdt enabled for wakeup. xres current sid307 i dd_xr supply current while xres asserted. this does not include current drawn due to the xres internal pull-up resistor. C30C a power source = vsys = 3.3 v, type-c device not attached, t a = 25 c note 2. if vddio > vddd, gpio p2.4 cannot be used. it must be left un connected. see tab l e 2 for pin numbers.
ez-pd? ccg3 document number: 002-03288 rev. *j page 25 of 45 i/o table 5. ac specifications (g uaranteed by characterization) spec id parameter description min typ max units details/conditions sid.clk#4 f cpu cpu input frequency dc C 48 mhz all vddd sid.pwr#20 t sleep wakeup from sleep mode C 0 C s C sid.pwr#21 t deepsleep wakeup from deep sleep mode C C 35 s C sid.xres#5 t xres external reset pulse width 5 C C s all vddio sys.fes#1 t _pwr_rdy power-up to ready to accept i 2 c/cc command C 5 25 ms C table 6. i/o dc specifications spec id parameter description min typ max units details/conditions sid.gio#37 v ih_cmos input voltage high threshold 0.7 vddio C C v cmos input sid.gio#38 v il_cmos input voltage low threshold C C 0.3 vddio v cmos input sid.gio#39 v ih_vddio2.7- lvttl input, vddio < 2.7 v 0.7 vddio C C v C sid.gio#40 v il_vddio2.7- lvttl input, vddio < 2.7 v C C 0.3 vddio v C sid.gio#41 v ih_vddio2.7+ lvttl input, vddio ? 2.7 v 2.0 C C v C sid.gio#42 v il_vddio2.7+ lvttl input, vddio ? 2.7 v C C 0.8 v C sid.gio#33 v oh_3v output voltage high level vddio C0.6 C C v i oh = 4 ma at 3v vddio sid.gio#34 v oh_1.8v output voltage high level vddio C0.5 C C v i oh = 1 ma at 1.8v vddio sid.gio#35 v ol_1.8v output voltage low level C C 0.6 v i ol = 4 ma at 1.8v vddio sid.gio#36 v ol_3v output voltage low level C C 0.6 v i ol = 4 ma at 3v vddio for sbu and aux pins sid.gio#5 r pu pull-up resistor value 3.5 5.6 8.5 k ? +25 c t a , all vddio sid.gio#6 r pd pull-down resistor value 3.5 5.6 8.5 k ? +25 c t a , all vddio sid.gio#16 i il input leakage current (absolute value) CC2na +25 c t a , all vddio. guaranteed by characterization. sid.gio#17 c pin max pin capacitance C 3.0 7 pf all vddio, all packages, all i/os except sbu and aux. guaranteed by characterization. sid.gio#17a c pin_sbu max pin capacitance C 16 18 pf all vddio, all packages, sbu pins only. guaranteed by characterization. sid.gio#17b c pin_aux max pin capacitance C 12 14 pf all vddio, all packages, aux pins only. guaranteed by characterization. sid.gio#43 v hysttl input hysteresis, lvttl vddio ? 2.7 v 15 40 C mv guaranteed by characterization sid.gio#44 v hyscmos input hysteresis cmos 0.05 vddio C C mv vddio < 4.5 v. guaranteed by characteri- zation. sid69 i diode current through protection diode to vddio/vss CC100 a guaranteed by characteri- zation sid.gio#45 i tot_gpio maximum total sink chip current CC85ma guaranteed by characteri- zation
ez-pd? ccg3 document number: 002-03288 rev. *j page 26 of 45 xres digital peripherals the following specifications apply to the timer/counter/pwm per ipherals in the timer mode. pulse width modulation (pwm) for gpio pins ovt sid.gio#46 i ihs input current when pad > vddio for ovt inputs CC10.00 aper i 2 c specification table 7. i/o ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid70 t risef rise time in fast strong mode 2 C 12 ns 3.3 v vddio, c load = 25 pf sid71 t fallf fall time in fast strong mode 2 C 12 ns 3.3 v vddio, c load = 25 pf table 6. i/o dc specifications (continued) spec id parameter description min typ max units details/conditions table 8. xres dc specifications spec id parameter description min typ max units details/conditions sid.xres#1 v ih_xres input voltage high threshold on xres pin 0.7 vddio C C v cmos input sid.xres#2 v il_xres input voltage low threshold on xres pin C C 0.3 vddio v cmos input sid.xres#3 c in_xres input capacitance on xres pin CC7pf guaranteed by charac- terization sid.xres#4 v hysxres input voltage hysteresis on xres pin C 0.05 vddio C mv guaranteed by charac- terization table 9. pwm ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid.tcpwm.3 t cpwmfreq operating frequency C C fc mhz fc max = clk_sys. maximum = 48 mhz. sid.tcpwm.4 t pwmenext input trigger pulse width 2/fc C C ns for all trigger events sid.tcpwm.5 t pwmext output trigger pulse width 2/fc C C ns minimum possible width of overflow, underflow, and cc (counter equals compare value) outputs sid.tcpwm.5a t cres resolution of counter 1/fc C C ns minimum time between successive counts sid.tcpwm.5b pwm res pwm resolution 1/fc C C ns minimum pulse width of pwm output sid.tcpwm.5c q res quadrature inputs resolution 1/fc C C ns minimum pulse width between quadrature-phase inputs
ez-pd? ccg3 document number: 002-03288 rev. *j page 27 of 45 i 2 c table 10. fixed i 2 c dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid149 i i2c1 block current consumption at 100 khz C C 60 aC sid150 i i2c2 block current consumption at 400 khz C C 185 aC sid151 i i2c3 block current consumption at 1 mbps C C 390 aC sid152 i i2c4 i 2 c enabled in deep sleep mode C C 1.4 aC table 11. fixed i 2 c ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid153 f i2c1 bit rate C C 1 mbps C table 12. fixed uart dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid160 i uart1 block current consumption at 100 kb/s C C 125 a C sid161 i uart2 block current consumption at 1000 kb/s CC312a C table 13. fixed uart ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid162 f uart bit rate C C 1 mbps C table 14. fixed sp i dc specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid163 i spi1 block current consumption at 1 mb/s C C 360 a C sid164 i spi2 block current consumption at 4 mb/s C C 560 a C sid165 i spi3 block current consumption at 8 mb/s C C 600 a C table 15. fixed spi ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid166 f spi spi operating frequency (master; 6x oversampling) CC8mhz C table 16. fixed spi maste r mode ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid167 t dmo mosi valid after sclock driving edge C C 15 ns C sid168 t dsi miso valid before sclock capturing edge 20 C C ns full clock, late miso sampling sid169 t hmo previous mosi data hold time 0 C C ns referred to slave capturing edge
ez-pd? ccg3 document number: 002-03288 rev. *j page 28 of 45 system resources power-on-reset (por) with brown out swd interface table 17. fixed spi slave mode ac specifications (guaranteed by characterization) spec id parameter description min typ max units details/conditions sid170 t dmi mosi valid before sclock capturing edge 40 C C ns C sid171 t dso miso valid after sclock driving edge C C 42 + 3 t cpu ns t cpu = 1/f cpu sid171a t dso_ext miso valid after sclock driving edge in ext clk mode CC 48 ns C sid172 t hso previous miso data hold time 0 C C ns C sid172a t sselsck ssel valid to first sck valid edge 100 C C ns C table 18. imprecise power on r eset (pres) (guaranteed by chara cterization) spec id parameter description min typ max units details/conditions sid185 v riseipor power-on reset (por) rising trip voltage 0.80 C 1.50 v C sid186 v fallipor por falling trip voltage 0.70 C 1.4 v C table 19. precise power on reset (por) (guaranteed by characte rization) spec id parameter description min typ max units details/conditions sid190 v fallppor brown-out detect (bod) trip voltage in active/sleep modes 1.48 C 1.62 v C sid192 v falldpslp bod trip voltage in deep sleep mode 1.1 C 1.5 v C table 20. swd interface specifications spec id parameter description min typ max units details/conditions sid.swd#1 f_swdclk1 3.3 v ? vddio ? 5.5 v C C 14 mhz swdclk ?? 1/3 cpu clock frequency sid.swd#2 f_swdclk2 1.8 v ? vddio ? 3.3 v C C 7 mhz swdclk ?? 1/3 cpu clock frequency sid.swd#3 t_swdi_setup t = 1/f swdclk 0.25 t C C ns guaranteed by characterization sid.swd#4 t_swdi_hold t = 1/f swdclk 0.25 t C C ns guaranteed by characterization sid.swd#5 t_swdo_valid t = 1/f swdclk C C 0.50 t ns guaranteed by characterization sid.swd#6 t_swdo_hold t = 1/f swdclk 1 C C ns guaranteed by characterization
ez-pd? ccg3 document number: 002-03288 rev. *j page 29 of 45 internal main oscillator internal low-speed oscillatorpower down table 21. imo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid218 i imo1 imo operating current at 48 mhz C C 1000 aC table 22. imo ac specifications spec id parameter description min typ max units details/conditions sid.clk#13 f imotol frequency variation at 24, 36, and 48 mhz (trimmed) C C 2 % C25 c ?? t a ?? 85 c, all vddd sid226 t startimo imo start-up time C C 7 s guaranteed by characterization sid229 t jitrmsimo2 rms jitter at 24 mhz C 145 C ps guaranteed by characterization sid.clk#1 f imo imo frequency 24 C 48 mhz all vddd table 23. ilo dc specifications (guaranteed by design) spec id parameter description min typ max units details/conditions sid231 i ilo1 i lo operating current C 0.3 1.05 a C sid233 i iloleak i lo leakage current C 2 15 na C table 24. ilo ac specifications spec id parameter description min typ max units details/conditions sid234 t startilo1 i lo start-up time C C 2 ms guaranteed by characterization sid238 t iloduty i lo duty cycle 40 50 60 % guaranteed by characterization sid.clk#5 f ilo i lo frequency 20 40 80 khz C table 25. pd dc specifications spec id parameter description min typ max units details/conditions sid.pd.1 r p _std dfp cc termination for default usb power 64 80 96 a C sid.pd.2 r p _1.5a dfp cc termination for 1.5a power 166 180 194.4 a C sid.pd.3 r p _3.0a dfp cc termination for 3.0a power 304 330 356.4 a C sid.pd.4 r d ufp cc termination 4.59 5.1 5.61 k? C sid.pd.5 r d _db ufp dead battery cc termination on cc1 and cc2, valid for 1.5a and 3.0a r p termination values 4.08 5.1 6.12 k? ufp dead battery cc termination on cc1 and cc2. for default r p termination, the voltage on cc1 and cc2 is guaranteed to be <1.32 v. sid.pd.6 r a emca cable termination 0.8 1.0 1.2 k? all supplies forced to 0 v and 0.2 v applied at vconn. sid.pd.7 r a _off emca cable termination - disabled 0.4 0.75 C m? 2.7 v applied at vconn with r a disabled.
ez-pd? ccg3 document number: 002-03288 rev. *j page 30 of 45 gate driver specifications sid.pd.8 r leak_1 vconn leaker for 0.1-f load C C 216 k? managed active cable (mac) discharge. sid.pd.9 r leak_2 vconn leaker for 0.5-f load C C 43.2 k? sid.pd.10 r leak_3 vconn leaker for 1.0-f load C C 21.6 k? sid.pd.11 r leak_4 vconn leaker for 2.0-f load C C 10.8 k? sid.pd.12 r leak_5 vconn leaker for 5.0-f load C C 4.32 k? sid.pd.13 r leak_6 vconn leaker for 10-f load C C 2.16 k? sid.pd.14 i leak leaker on vconn for discharge upon cable detach 150 C 550 a C sid.pd.15 v gndoffset ground offset tolerated by bmc receiver C400 C 400 mv relative to the remote bmc transmitter. guaranteed by characterization. table 26. csa specifications spec id parameter description min typ max units details/conditions sid.csa.1 out_e_trim_15_ds overall error at av = 15 using deep sleep reference C7.00 C 7.00 % guaranteed by characterization. sid.csa.2 out_e_trim_15_bg overall error at av = 15 using bandgap reference C4.50 C 4.50 % guaranteed by characterization. sid.csa.3 out_e_trim_100 overall error at av = 100 using either bandgap or deep sleep reference C24.50 C 24.50 % C table 27. uv/ov specifications spec id parameter description min typ max units details/conditions sid.uvov.1 v thuvov1 voltage threshold accuracy, v bus ? 16 v C6 6 % tested at vbus = 3.75 v, 4.5 v, 5.25 v, 12 v, 16 v sid.uvov.2 v thuvov2 voltage threshold accuracy, v bus ? 16 v C10 10 % tested at vbus = 20 v table 25. pd dc specifications (continued) spec id parameter description min typ max units details/conditions table 28. gate driver dc specifications spec id parameter description min typ max units details/conditions dc.ngdo.1 vgs1 gate to source overdrive 5 C 16.5 v 1. gate driver supply voltage ? 5v, where gate driver supply voltage = vbus _p for vbus_p_ctrl_ out puts, and vbus_c for vbus_c_ctrl_ outputs. 2. gate driver current = 0 3. gate driver configuration = nfet 4. gate driver pump clock divider = 1 dc.ngdo.2 vgs2 gate to source overdrive 3.75 C 16.5 v 1. gate driver supply voltage ? 3.75v, where gate driver supply voltage = vbus _p for vbus_p_ctrl_ out puts, and vbus_c for vbus_c_ctrl_ outputs. 2. gate driver current = 0 3. gate driver configuration = nfet 4. gate driver pump clock divider = 1 dc.ngdo.6 r pd resistance when pull down enabled C C 5 k ? C
ez-pd? ccg3 document number: 002-03288 rev. *j page 31 of 45 sbu charger detect table 29. gate driver ac specifications spec id parameter description min typ max units details/conditions ac.ngdo.1 t on gate turn-on time to gate_driver_sup- ply_voltage + 5v for supply voltage ? 5v and vbus * 2 for supply voltage < 5v C C 1 ms 1. gate driver configuration = nfet 2. load = the gate of a si9936 mosfet table 30. analog crossbar switch specifications spec id parameter description min typ max units details/conditions sid.sbu.1 ron_sw switch on resistance C C 10 voltage input from 0 v to 3.6 v sid.sbu.2 rpu_aux_1 aux_p/n pull-up resistance C 100k 80 C 120 k C sid.sbu.3 rpu_aux_2 aux_p/n pull- up resistance C 1m 0.8 C 1.2 m C sid.sbu.4 rpd_aux_1 aux_p/n pull-down resistance C 100k 80 C 120 k C sid.sbu.5 rpd_aux_2 aux_p/n pull-down resistance C 1m 0.8 C 1.2 m C sid.sbu.6 rpd_aux_3 aux_p/n pull-down resistance C 470k 329 C 611 k C sid.sbu.7 rpd_aux_4 aux_p/n pull-down resistance C 4.7m 3.29 C 6.11 m ?C table 31. charger detect specifications spec id parameter description min typ max units details/conditions sid.cd.1 vdat_ref bc1.2 data detect voltage threshold 250 C 400 mv C sid.cd.2 vdm_src bc1.2 dm voltage source 500 C 700 mv with current sink of 25 aC175 a sid.cd.3 vdp_src bc1.2 dp voltage source 500 C 700 mv with current sink of 25 aC175 a sid.cd.4 idm_sink bc1.2 dm current sink 25 C 175 a C sid.cd.5 idp_sink bc1.2 dp current sink 25 C 175 a C sid.cd.6 idp_src bc1.2 dp dcd current source 7 C 13 a C sid.cd.7 rdp_up usb fs dp pull-up termination 0.9 C 1.575 k C sid.cd.8 rdm_up usb fs dm pull-up termination 0.9 C 1.575 k C sid.cd.9 rdp_dwn usb fs dp pull-down termination 14.25 C 24.8 k C sid.cd.10 rdm_dwn usb fs dm pull-down termination 14.25 C 24.8 k C sid.cd.11 rdat_lkg dp/dm data line leakage termination 300 C 500 k the charger detect function and data line leakage is enabled. sid.cd.12 rdcp_dat bc1.2 dcp port resistance between dp and dm CC40 C sid.cd.13 vseth usb fs logic threshold 1.26 C 1.54 v C
ez-pd? ccg3 document number: 002-03288 rev. *j page 32 of 45 analog to digital converter table 32. adc dc specifications (guaranteed by characterizatio n) spec id parameter description min typ max units details/conditions sid.adc.1 resolution adc resolution C 8 C bits C sid.adc.2 inl integral non-linearity C1.5 C 1.5 lsb C sid.adc.3 dnl differential non-linearity C2.5 C 2.5 lsb C sid.adc.4 gain error gain error C1 C 1 lsb C table 33. adc ac specificati ons (guaranteed by design) spec id parameter description min typ max units details/conditions sid.adc.5 slew_max rate of change of sampled voltage signal CC3v/ms C table 34. vbus_c regul ator dc specifications spec id parameter description min typ max units details/conditions sid.20vreg.1 vbusreg vbus regulator output voltage measured at vddd for vbus = 4.5 v to 21.5 v 3C3.6v vbus = 4.5 v - 21.5 v range. vddd voltage measured with no load and a load of 30 ma. sid.20vreg.2 vbusreg2 vbus regulator output voltage measured at vddd for vbus = 3.5 v to 21.5 v 3C3.6v vbus = 4.5 v - 21.5 v range. vddd voltage measured with no load and a load of 15 ma. sid.20vreg.6 vbuslinreg vbus regulator line regulation for vbus from 4.5 v to 21.5 v CC0.5%/v vbus supply varied from 4.5 v to 21.5 v and the change in the vddd measured. guaranteed by characterization. sid.20vreg.8 vbusloadreg vbus regulator load regulation for vbus from 4.5 v to 21.5 v CC0.2%/ma supply of 4.5 v - 21.5 v applied on vbus and the load current swept from 0 to 30 ma. the change in vddd is measured. guaranteed by characterization. table 35. vbus_c regulator ac sp ecifications (guaranteed by ch aracterization) spec id parameter description min typ max units details/conditions ac.20vreg.1 t start regulator start-up time C C 120 s apply vbus and measure start time on vddd pin. ac.20vreg.2 t stop regulator power down time C C 1 s time from assertion of an internal disable signal to for load current on vddd to decrease from 30 ma to 10 a. table 36. vsys switch specification spec id parameter description min typ max units details/conditions sid.vddsw.1 res_sw resistance from vsys supply input to the output supply vddd CC1.5? measured with a load current of 5 ma - 10 ma on vddd.
ez-pd? ccg3 document number: 002-03288 rev. *j page 33 of 45 memory table 37. flash ac specifications spec id parameter description min typ max units details/conditions sid.mem#3 flash_erase row erase time C C 15.5 ms C sid.mem#4 flash_write row (block) write time (erase and program) CC20 ms C sid.mem#8 flash_row_pgm row program time after erase C C 7 ms C sid178 tbulkerase bulk erase time (64k bytes) C C 35 ms C sid180 tdevprog total device progra m time C C 7.5 s guaranteed by char acterization sid182 fret1 flash retention, t a 55 c, 100 k p/e cycles 20 C C years guaranteed by characterization sid182a fret2 flash retention, t a 85 c, 10 k p/e cycles 10 C C years guaranteed by characterization sid182b fret3 flash retention, t a 105 c, 10 k p/e cycles 3 C C years guaranteed by characterization
ez-pd? ccg3 document number: 002-03288 rev. *j page 34 of 45 ordering information table 38 lists the ez-pd ccg3 part numbers and features. ordering code definitions notes 3. termination resistor denoting an emca. 4. termination resistor denoting an upstream facing port. 5. termination resistor denoting a downstream facing port. 6. termination resistor denoting dead battery termination. 7. the cypd3135 parts are shipped with bootloader and applicatio n firmware with limited functionality. its purpose is to facili tate application flashing over cc line using the ez-pd configuration utility. the power adapter requires an explicit power contract to be negotiated prior to enabling the ez-pd configuration utility to flash the application firmware. this application firmware, based on the s tate of the gpio (p1.0), determines the type of provider load s witch (nfet/pfet) and supplies the 5v vbus over type-c. table 38. ez-pd ccg3 ordering information part number application termination resistor role default fw package si id CYPD3120-40LQXIT dongle r p , r d [4] , r d_db ufp usb bootloader and application fw 40-qfn 1d00 cypd3120-40lqxi cypd3121-40lqxit power banks r p [5] , r d , r d_db [6] drp usb bootloader 40-qfn 1d02 cypd3121-40lqxi cypd3122-40lqxit monitor (dfp) r p , r d , r d_db dfp i 2 c bootloader 40-qfn 1d03 cypd3122-40lqxi cypd3123-40lqxit charge-through dongle r p , r d , r d_db drp usb bootloader and application fw 40-qfn 1d09 cypd3123-40lqxi cypd3125-40lqxit notebooks, smartphones r p , r d , r d_db drp i 2 c bootloader 40-qfn 1d04 cypd3125-40lqxi cypd3126-42fnxit drp r p , r d [4] , r d_db drp i 2 c bootloader 42-csp 1d07 cypd3135-32lqxqt power adapter r p dfp cc bootloader and application fw [7] 32-qfn 1d08 cypd3135-32lqxq cypd3135-40lqxit power adapter r p dfp cc bootloader and application fw [7] 40-qfn 1d05 cypd3135-40lqxi cypd3135-40lqxqt power adapter r p dfp cc bootloader and application fw [7] 40-qfn 1d05 cypd3135-40lqxq t = tape and reel temperature grade: i = industrial (C40 c - 85 c), q = extended industrial (C40 c - 105 c) lead: x = pb-free package type: fn = csp; lq = qfn number of pins in the package application and feature combination designation number of type-c ports: 1 = 1 port, 2 = 2 port product type: 3 = third-generation product family, ccg3 marketing code: pd = power delivery product family company id: cy = cypress cy xx pd x x xx xx - x x x
ez-pd? ccg3 document number: 002-03288 rev. *j page 35 of 45 packaging table 39. package characteristics parameter description conditions min typ max units t a operating ambient temperature industrial C40 25 85 c extended industrial 105 c t j operating junction temperature industrial C40 25 100 c extended industrial 125 c t ja package ? ja (40-pin qfn) C C C 17 c/w t jc package ? jc (40-pin qfn) C C C 2 c/w t ja package ? ja (42-ball wlcsp) C C C 34 c/w t jc package ? jc (42-ball wlcsp) C C C 0.3 c/w t ja package ? ja (32-pin qfn) C C C 18 c/w t jc package ? jc (32-pin qfn) C C C 4 c/w table 40. solder reflow peak temperature package maximum peak temperature maximum time withi n 5 c of peak temperature 40-pin qfn 260 c 30 seconds 42-ball wlcsp 260 c 30 seconds 32-pin qfn 260 c 30 seconds table 41. package moisture sens itivity level (msl), ipc/jedec j-std-2 package msl 42-ball wlcsp msl 1 40-pin qfn msl 3 32-pin qfn msl 3
ez-pd? ccg3 document number: 002-03288 rev. *j page 36 of 45 figure 17. 40-pin qfn p ackage outline, 001-80659 figure 18. 42-ball csp package outline, 002-04062 001-80659 *a 002-04062 *a
ez-pd? ccg3 document number: 002-03288 rev. *j page 37 of 45 figure 19. 32-pin qfn p ackage outline, 001-42168 bottom view top view side view see note 1 4. dimensions are in millimeters 2. based on ref jedec # mo-248 notes: 1. hatch area is solderable exposed pad 3. package weight: 0.0388g dimensions nom. min. b e d a a1 - symbol max. 0.60 0.045 0.50 typ l 0.18 0.25 0.30 e2 d2 e 0.40 0.30 0.50 3.40 3.50 3.60 a2 0.15 bsc 4.90 5.00 5.10 4.90 5.00 5.10 3.40 3.50 3.60 0.55 0.50 0.020 001-42168 *f
ez-pd? ccg3 document number: 002-03288 rev. *j page 38 of 45 acronyms table 42. acronyms used in this document acronym description adc analog-to-digital converter aes advanced encryption standard ahb amba (advanced microcontroller bus architecture) high-performance bus api application programming interface arm ? advanced risc machine, a cpu architecture bmc biphase mark code cc configuration channel ccg3 cable controller generation 3 cpu central processing unit crc cyclic redundancy check, an error-checking protocol cs current sense dfp downstream facing port dio digital input/output, gpio with only digital capabil- ities, no analog. see gpio. drp dual role port eeprom electrically erasable programmable read-only memory emca electronically marked cable assembly, a usb cable that includes an ic that reports cable characteristics (e.g., current rating) to the type-c ports emi electromagnetic interference esd electrostatic discharge fs full-speed gpio general-purpose input/output hpd hot plug detect ic integrated circuit ide integrated development environment i 2 c, or iic inter-integrated circuit, a communications protocol ilo internal low-speed oscillator, see also imo imo internal main oscillator, see also ilo ioss input/output subsystem i/o input/output, see also gpio ldo low-dropout regulator lvd low-voltage detect lvttl low-voltage transistor-transistor logic mcu microcontroller unit mmio memory mapped input/output nc no connect nmi nonmaskable interrupt nvic nested vectored interrupt controller opamp operational amplifier ocp overcurrent protection ovp overvoltage protection pcb printed circuit board pd power delivery pga programmable gain amplifier phy physical layer por power-on reset pres precise power-on reset psoc ? programmable system-on-chip? pwm pulse-width modulator ram random-access memory risc reduced-instruct ion-set computing rms root-mean-square rtc real-time clock rx receive sar successive approx imation register scb serial communication block scl i 2 c serial clock sda i 2 c serial data s/h sample and hold sha secure hash algorithm spi serial peripheral interface, a communications protocol sram static random access memory swd serial wire debug, a test protocol tcpwm timer/counter pulse-width modulator thunder- bolt ? trademark of intel tx transmit type-c a new standard with a slimmer usb connector and a reversible cable, capable of sourcing up to 100 w of power uart universal asynchronous transmitter receiver, a communications protocol usb universal serial bus usb pd usb power delivery usb-fs usb full-speed usbio usb input/output, ccg2 pins used to connect to a usb port usbpd ss usb pd subsystem vdm vendor defined messages xres external reset i/o pin table 42. acronyms used in this document (continued) acronym description
ez-pd? ccg3 document number: 002-03288 rev. *j page 39 of 45 document conventions units of measure table 43. units of measure symbol unit of measure c degrees celsius hz hertz kb 1024 bytes khz kilohertz k ? kilo ohm mbps megabits per second mhz megahertz m ? mega-ohm msps megasamples per second a microampere f microfarad s microsecond v microvolt w microwatt ma milliampere ms millisecond mv millivolt na nanoampere ns nanosecond ? ohm pf picofarad ppm parts per million ps picosecond s second sps samples per second vvolt
ez-pd? ccg3 document number: 002-03288 rev. *j page 40 of 45 references and links to a pplications collaterals knowledge base articles key differences among ez-pd? ccg1, ccg2, ccg3 and ccg4 - kba210740 programming ez-pd? ccg2, ez-pd? ccg3 and ez-pd? ccg4 using psoc? programme r and miniprog3 - kba96477 ccgx frequently asked questions (faqs) - kba97244 handling precautions for cy4501 ccg1 dvk - kba210560 cypress ez-pd? ccgx hardware - kba204102 difference between usb type -c and usb-pd - kba204033 ccgx programming methods - kba97271 getting started with cypress usb type-c products - kba04071 type-c to displayport cable electrical requirements dead battery charging implementation in usb type-c solutions - kba97273 termination resistors required for the usb type-c connector C kba97180 vbus bypass capacitor recommendation for type-c cable and type-c to legacy cable/adapter assemblies C kba97270 need for regulator and auxiliary switch in type-c to displayport (dp) cable solution - kba97274 need for a usb billboard device in type-c solutions C kba97146 ccg1 devices in type-c to l egacy cable/adapter assemblies C kba97145 cypress usb type-c controller supported solutions C kba97179 termination resistors for type-c to legacy ports C kba97272 handling instructions for cy4502 ccg2 development kit C kba97916 thunderbolt? cable application using ccg3 devices - kba210976 power adapter application using ccg3 devices - kba210975 methods to upgrade firmware on ccg3 devices - kba210974 device flash memory size and advantages - kba210973 applications of ez-pd? ccg4 - kba210739 application notes an96527 - designing usb type-c products using cypresss ccg1 controllers an95615 - designing usb 3.1 type-c cables using ez-pd? ccg2 an95599 - hardware design guidelines for ez-pd? ccg2 an210403 - hardware design guidelines for dual role port applications using ez-pd? usb type-c controllers an210771 - getting started with ez-pd? ccg4 reference designs ez-pd? ccg2 electronically marked cable assembly (emca) paddle card reference design ez-pd? ccg2 usb type-c to displayport cable solution ccg1 usb type-c to displayport cable solution ccg1 usb type-c to hdmi/dv i/vga adapter solution ez-pd? ccg2 usb type-c to hdmi adapter solution ccg1 electronically marked cable assembly (emca) paddle card reference design ccg1 usb type-c to legacy usb device cable paddle card reference schematics ez-usb gx3 usb type-c to gigabit ethernet dongle ez-pd? ccg2 usb type-c monitor/dock solution ccg2 20w power adapter reference design ccg2 18w power adapter reference design ez-usb gx3 usb type-a to gigabit ethernet reference design kit kits cy4501 ccg1 development kit cy4502 ez-pd? ccg2 development kit cy4531 ez-pd ccg3 evaluation kit cy4541 ez-pd? ccg4 evaluation kit datasheets ccg1 datasheet: usb type-c port controller with power delivery cypd1120 datasheet: usb power delivery alternate mode controller on type-c ccg2: usb type-c port controller datasheet ccg4: two-port usb type-c controller datasheet
ez-pd? ccg3 document number: 002-03288 rev. *j page 41 of 45 document history page document title: ez -pd? ccg3 usb type -c port controller document number: 002-03288 revision ecn orig. of change submission date description of change ** 4905678 vgt 09/11/2015 new data sheet. *a 4953333 vgt 10/08/2015 updated general description : updated the number of gpios to 20. updated functional overview : updated gpio : updated the number of gpios to 20. updated pinouts : updated table 2 . updated figure 4 . added figure 6 . *b 5007726 vgt 11/25/2015 changed status from advance to preliminary. updated features . added ez-pd ccg3 block diagram . updated functional overview : updated usb-pd subsystem (usbpd ss) (updated description). added full-speed usb subsystem . updated pinouts : updated table 2 . updated figure 4 . updated figure 6 . added applications . updated electrical specifications : updated absolute maximum ratings : updated table 3 . updated device-level specifications : updated table 4 . updated table 5 . updated i/o : updated table 6 . updated xres : updated table 8 . updated system resources : updated power-on-reset (p or) with brown out swd interface : updated table 18 . updated table 19 . updated table 20 . updated internal main oscillator : updated table 22 . updated internal low-speed oscillatorpower down : updated table 23 . updated table 24 . updated internal low-speed oscillatorpower down : updated table 25 .
ez-pd? ccg3 document number: 002-03288 rev. *j page 42 of 45 *b (cont.) 5007726 vgt 11/25/2015 updated analog to digital converter : updated table 32 . updated table 33 . updated packaging : added figure 18 (spec 002-04062 *a). *c 5080470 vgt 01/11/2016 updated general description . updated features . updated logic block diagram . updated power systems overview . updated pinouts : updated table 2 . added table ccg3 pin descrip tion for 16-soic device. added figure pinout of 16-soic package (top view). updated applications : updated figure . updated figure 11 . updated figure power adapter application diagram (16-soic devi ce). updated figure 15 . updated ordering information . updated packaging : added spec 51-85022 *e. added errata. *d 5137796 vgt 03/09/2016 updated pinouts : updated table ccg3 pin description for 16-soic device. updated figure pinout of 16-soic package (top view). updated applications : updated figure 11 . updated figure 12 . updated ordering information updated errata. updated to new template. *e 5240836 vgt 04/28/2016 updated general description : updated description. updated features : updated type-c and usb-pd support : updated description. updated packages : updated description. updated logic block diagram . updated functional overview : updated integrated billboard device : updated description. updated usb-pd subsystem (usbpd ss) : updated description. added figure 2 and figure 5 . document history page (continued) document title: ez -pd? ccg3 usb type -c port controller document number: 002-03288 revision ecn orig. of change submission date description of change
ez-pd? ccg3 document number: 002-03288 rev. *j page 43 of 45 *e (cont.) 5240836 vgt 04/28/2016 updated power systems overview : updated description. updated figure 3 . updated pinouts : updated table 2 : updated details in description column corresponding to vddio pin. removed table ccg3 pin description for 16-soic device. removed figure pinout of 16-soic package (top view). updated applications : removed figure power adapter application diagram (16-soic device). added figure 12 . updated electrical specifications : updated device-level specifications : updated table 4 . updated details in details/conditions column corresponding to sid.pwr#1_a spec id and v sys parameter. replaced v ddd with 5.5 in max column corresponding to sid.pwr#13 spec id and v ddio parameter. added sid.pwr#13_a spec id corresponding to v ddio parameter and its details. added sid.pwr#1_c and sid.pwr#1_d spec ids corresponding to v sys parameter and its details. replaced enabled with disabled in details/conditions colu mn corresponding to sid.pwr#28 spec id and v bus parameter. updated details in description and details/conditions colum ns corresponding to sid307 spec id and i dd_xr parameter. updated system resources : added gate driver specifications , charger detect . updated ordering information : updated part numbers. updated details in application column corresponding to part n umber cypd3121-40lqxit. updated ordering code definitions updated packaging : removed spec 51-85022 *e. removed errata. *f 5342389 vgt 07/28/2016 added available firmware and software tools , ccg3 programming and bootloading , and references and links to applications collaterals . added descriptive notes for the application diagrams. updated features , applications and timer/counter/pwm block (tcpwm) . updated table 2 through table 6 , ta b l e 1 8 , ta b l e 1 9 , ta b l e 2 2 , table 23 , table 25 , and table 31 through ta b l e 3 8 . updated figure 7 , figure 8 , figure , figure 11 , and figure 19 (package diagram spec 001-42168 *e). added figure 5 , figure 13 , and figure 14 . added ta b l e 2 6 , table 27 , ta b l e 3 7 , and ta b l e 3 9 through table 41 . added vdm in acronyms . updated cypress logo and copyright information. *g 5449433 vgt 09/26/2016 added ta b l e 3 4 through table 36 . updated table 3 , table 4 , ta b l e 6 , and table 37 . updated copyright and disclaimer. added compliance information in sales, solutions, and legal information . document history page (continued) document title: ez -pd? ccg3 usb type -c port controller document number: 002-03288 revision ecn orig. of change submission date description of change
ez-pd? ccg3 document number: 002-03288 rev. *j page 44 of 45 *h 5514508 vgt 01/13/2017 removed preliminary document status. updated sales information and copyright details. added gate driver specifications in table 28 and ta b l e 2 9 . updated applications . added figure 16 . updated ordering information : added cypd3123-40lqxit part number. removed cypd3105-42fnxit part number. *i 5662219 vgt 03/29/2017 updated table 2 , added non tape and reel part numbers and note 7 in table 38 , updated description prior to figure 11 . *j 6032274 vgt 2/21/2018 updated description of v5v pin in ta b l e 2 . removed parameter sid.pwr#13_a from ta b l e 4 . updated description in usb-pd subsystem (usbpd ss) . updated packaging : 32-pin qfn package outline, 001-42168 (*e to *f). document history page (continued) document title: ez -pd? ccg3 usb type -c port controller document number: 002-03288 revision ecn orig. of change submission date description of change
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